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DATA SHEET
MOS INTEGRATED CIRCUIT
PD485506
LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
Description
The PD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either 5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power consumption. The PD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and digital copiers. Moreover, the PD485506 can execute read and write operations independently on an asynchronous basis. Thus the PD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for the synchronization of multiple input signals. There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping).
Features
* 5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode) * Asynchronous read/write operations available * Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns) 15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns) * Power supply voltage VCC = 5.0 V 0.5 V * Suitable for sampling two lines of A3 size paper (16 dots/mm) * All input/output TTL compatible * 3-state output * Full static operation; data hold time = infinity
Ordering Information
Part Number R/W Cycle Time 25 ns 35 ns Package 44-pin plastic TSOP (II) (10.16 mm (400))
PD485506G5-25-7JF PD485506G5-35-7JF
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10060EJ7V0DSJ1 (7th edition) Date Published December 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1994
PD485506
Pin Configuration (Marking side)
44-pin plastic TSOP (II) (10.16 mm (400)) [PD485506G5-7JF]
DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 OE RE GND RSTR RCK VCC DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 WE MD GND RSTW WCK VCC DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15
DIN0 to DIN15 WCK RCK WE RE OE RSTW RSTR MD VCC GND Remark
: Data Inputs : Write Clock Input : Read Clock Input : Write Enable Input : Read Enable Input : Output Enable Input : Reset Write Input : Reset Read Input : Mode Set Input : +5.0 V Power Supply : Ground
DOUT0 to DOUT15 : Data Outputs
Refer to Package Drawing for the 1-pin index mark.
2
Data Sheet M10060EJ7V0DS00
PD485506
Block Diagram
VCC GND
RSTW WCK WE
Write Address Pointer
Read Address Pointer
RSTR RCK RE
DIN0 DIN1
Output Controller Input Controller
DOUT0 DOUT1 Memory Cell Array
Output Buffer Input Buffer
DIN2 DIN3 DIN4 DIN5 DIN6 DIN7
DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7
40,384 bits (5,048 words by 8 bits)
OE
DIN8 DIN9
Input Controller
DOUT8 DOUT9 Memory Cell Array 40,384 bits (5,048 words by 8 bits)
Output Controller
DIN10 DIN11 DIN12 DIN13 DIN14 DIN15
DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15
Mode Controller
MD
Output Buffer
Input Buffer
Data Sheet M10060EJ7V0DS00
3
PD485506
1. Input/Output Pin Function
Pin Pin Number 44 - 37, 30 - 23 1 - 8, 15 - 22 33 Symbol DIN0 | DIN15 DOUT0 | DOUT15 RSTW Reset Write Input Reset Read Input Write Enable Input Read Enable Input In Pin Name Data Input I/O Function
In
Write data input pins. The data inputs are strobed by the rising edge of WCK at the end of a cycle and the setup and hold times (tDS, tDH) are defined at this point. Read data output pins. The access time is regulated from the rising edge of RCK at the beginning of a cycle and defined by tAC. Reset input pin for the initialization of the write address pointer. The state of RSTW is strobed by the rising edge of WCK at the beginning of a cycle and the setup and hold times (tRS, tRH) are defined. Reset input pin for the initialization of the read address pointer. The state of RSTR is strobed by the rising edge of RCK at the beginning of a cycle and the setup and hold times (tRS, tRH) are defined. Write operation control signal input pin. When WE is in the disable mode ("H" level), the internal write operation is inhibited and the write address pointer stops at the current position. Read operation control signal input pin. When RE is in the disable mode ("H" level), the internal read operation is inhibited and the read address pointer stops at the current position. The data outputs remain valid for that address. Output operation control signal input pin. When OE is in the disable mode ("H" level), the data out is inhibited and the output changes to high impedance. The internal read operation is executed at that time and the read address pointer incremented in synchronization with the read clock. Write clock input pin. When WE is enabled ("L" level), the write operation is executed in synchronization with the write clock. The write address pointer is incremented simultaneously. Read clock input pin. When RE is enabled ("L" level), the read operation is executed in synchronization with the read clock. The read address pointer is incremented simultaneously. Mode set input pin. The level of MD gives the operation mode. When MD is in "L" level, 5,048 words by 16 bits configuration with DIN0 - DIN15, DOUT0 - DOUT15 is enabled. When MD is in "H" level, 10,096 words by 8 bits configuration with DIN0 - DIN7, DOUT0 - DOUT7 is enabled.
Data Output
Out
12
RSTR
In
36
WE
In
10
RE
In
9
OE
Output Enable Input
In
32
WCK
Write Clock Input
In
13
RCK
Read Clock Input
In
35
MD
Mode Set Input
In
4
Data Sheet M10060EJ7V0DS00
PD485506
2. Operation Mode
PD485506 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).
For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK). 2.1 Mode Set Cycle (5,048 words by 16 bits or 10,096 words by 8 bits organization)
PD485506 has a capability of selecting from two operation modes by judging the MD level when RSTW or
RSTR is enabled in the reset cycle.
MD Level "L" Bit Configuration 5,048 words by 16 bits Data Inputs/Outputs DIN0 - DIN15 DOUT0 - DOUT15 "H" 10,096 words by 8 bits DIN0 - DIN7 DOUT0 - DOUT7 Control Signal WCK, WE, RSTW RCK, RE, RSTR WCK, WE, RSTW RCK, RE, RSTR
Caution
Don't change the MD level during a reset cycle. (See Figure 4.6, 7, 8, 9 Mode Set Cycle Timing Chart)
5,048 Words by 16 Bits FIFO
WCK WE RSTW
DIN0 - DIN15
5,048 Words by 16 Bits
DOUT0 - DOUT15
RCK
RE
RSTR
OE
10,096 Words by 8 Bits FIFO
WCK WE RSTW
DIN0 - DIN7
10,096 Words by 8 Bits
DOUT0 - DOUT7
RCK
RE
RSTR
OE
Remark Fix DIN8 - DIN15 to "L" or "H" level in the 10,096 words by 8 bits mode.
Data Sheet M10060EJ7V0DS00
5
PD485506
2.2 Write Cycle When the WE input is enabled ("L" level), a write cycle is executed in synchronization with the WCK clock input. The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a oneline (5,048 bits or 10,096 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart. When WE is disabled ("H" level) in a write cycle, the write operatoin is not performed during the cycle which the WCK rising edge is in the WE = "H" level (tWEW). The WCK does not increment the write address pointer at this time. Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin incrementing again. 2.3 Read Cycle When the RE input is enabled ("L" level), a read cycle is executed in synchronization with the RCK clock input. When the OE input is also enabled ("L" level) at that time, data is output after tAC. Refer to Read Cycle Timing Chart. When RE is disabled ("H" level) in a read cycle, the read operation is not performed during the cycle which the RCK rising edge is in the RE = "H" level (tREW). The RCK does not increment the read address pointer at this time. 2.4 Write Reset Cycle/Read Reset Cycle After power up, the PD485506 requires the initialization of internal circuits because the read and write address pointers are not defined at that time. It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and RCK, and then input the RSTW and RSTR signals to initialize the circuit. Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write Reset Cycle Timing Chart, Read Reset Cycle Timing Chart. Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE, WE or OE.
6
Data Sheet M10060EJ7V0DS00
PD485506
Operation-related Restriction Following restriction exists to read data written in a write cycle. Read the written data after an elapse of 1/2 write cycle + tWAR since the write cycle ends (see Figure 2.1). If tWAR is not satisfied, the output data may undefined. Figure 2.1 Delay Bits Restriction Timing Chart
0 WCK
1
2
3
1/2 write cycle tWAR 0 RCK High impedance DIN High impedance DOUT 0 1 2 3 tAC 0 1 2 3 1 2
Remark This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR signals.
Data Sheet M10060EJ7V0DS00
7
PD485506
3. Electrical Specifications
All voltages are referenced to GND. Absolute Maximum Ratings
Parameter Voltage on any pin relative to GND Supply voltage Output current Operating ambient temperature Storage temperature Symbol VT VCC IO TA Tstg Condition Rating -0.5Note to VCC + 0.5 Unit V V mA C C
-0.5 to +7.0 20 0 to 70 -55 to +125
Note
-3.0 V MIN. (Pulse width = 10 ns) Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Caution
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 4.5 2.4 -0.3Note 0 TYP. 5.0 MAX. 5.5 VCC + 0.5 +0.8 70 Unit V V V C
Note
-3.0 V MIN. (Pulse width = 10 ns)
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current Input leakage current Output leakage current High level output voltage Low level output voltage Symbol ICC II IO VOH VOL VI = 0 to VCC, Other Input 0 V VO = 0 to VCC, DOUT: High impedance IOH = -1 mA IOL = 2 mA -10 -10 2.4 0.4 Test Condition MIN. TYP. MAX. 140 +10 +10 Unit mA
A A
V V
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Output capacitance Symbol CI CO Test Condition MIN. TYP. MAX. 10 10 Unit pF pF
8
Data Sheet M10060EJ7V0DS00
PD485506
AC Characteristics (Recommended Operating Conditions unless otherwise noted)Notes 1, 2, 3
Parameter Write clock cycle time Write clock pulse width Write clock precharge time Read clock cycle time Read clock pulse width Read clock precharge time Access time Write data-read delay time Output hold time Output low-impedance time Output high-impedance time Input data setup time Input data hold time MD Set setup time MD Set hold time MD Set time Output low-impedance time (Mode change) Output high-impedance time (Mode change) RSTW/RSTR Setup time RSTW/RSTR Hold time RSTW/RSTR Deselected time (1) RSTW/RSTR Deselected time (2) WE Setup time WE Hold time WE Deselected time (1) WE Deselected time (2) RE Setup time RE Hold time RE Deselected time (1) RE Deselected time (2) OE Setup time OE Hold time OE Deselected time (1) OE Deselected time (2) WE Disable time RE Disable time OE Disable time Write reset time Read reset time Transition time Symbol tWCK tWCW tWCP tRCK tRCW tRCP tAC tWAR tOH tLZ tHZ tDS tDH tMS tMH tMD tLZM tHZM tRS tRH tRN1 tRN2 tWES tWEH tWEN1 tWEN2 tRES tREH tREN1 tREN2 tOES tOEH tOEN1 tOEN2 tWEW tREW tOEW tRSTW tRSTR tT 470 5 5 5 7 3 20 10 0 5 5 7 3 3 7 7 3 3 7 7 3 3 7 7 3 3 7 0 0 0 0 0 3 35 18 18 18 18
PD485506-25
MIN. 25 11 11 25 11 11 18 MAX.
PD485506-35
MIN. 35 12 12 35 12 12 25 470 5 5 5 10 3 20 10 0 5 5 10 3 3 10 10 3 3 10 10 3 3 10 10 3 3 10 0 0 0 0 0 3 35 25 25 25 25 MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms ms ns
Notes
4 4
5 4 4 6 6 7 7 8 8 9 9 10 10 11 11 10 10 11 11
Data Sheet M10060EJ7V0DS00
9
PD485506
Notes 1. AC measurements assume tT = 5 ns. 2. AC Characteristics test condition Input Timing Specification
3.0 V 1.5 V 0V tT = 5 ns tT = 5 ns Test points
Output Timing Specification
2.0 V High impedance 0.8 V
Test points
High impedance
Output Loads for Timing
VCC 1.8 k DOUT DOUT VCC 1.8 k
1.1 k
30 pF
1.1 k
5 pF
(tAC,tOH)
(tLZ,tHZ)
3. Input timing reference levels = 1.5 V. Output timing reference levels; VOH = 2.0 V, VOL = 0.8 V. 4. tLZ, tHZ, tLZM and tHZM are measured at 200 mV from the steady state voltage. Under any conditions, tLZ tHZ and tLZM tHZM. 5. Mode set signal (MD) must be input synchronously with write reset signal (tRSTW period) or read reset signal (tRSTR period). Under this condition, tRSTW = tMD (tRSTR = tMD). 6. If either tRS or tRH is less than the specified value, reset operations are not guaranteed. 7. If either tRN1 or tRN2 is less than the specified value, reset operations may extend to cycles preceding or following the period of reset operations. 8. If either tWES or tWEH is less than the specified value, write disable operations are not guaranteed. 9. If either tWEN1 or tWEN2 is less than the specified value, internal write disable operations may extend to cycles preceding or following the period of write disable operations. 10. If either tRES or tREH, tOES or tOEH is less than the specified value, read disable operations are not guaranteed. 11. If either tREN1 or tREN2, tOEN1 or tOEN2 is less than the specified value, internal read disable operations may extend to cycles preceding or following the period of read disable operations.
10
Data Sheet M10060EJ7V0DS00
PD485506
Write Cycle Timing Chart
Cycle n tWCK tWCP WCK (Input) tWCW WE (Input) tWEW tDS DIN (Input) tDH (n) (n+1) tDS tDH (n+3) tWEN1 tWES tWEH tWEN2 Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3
(n+2)
Remark RSTW = "H" level Read Cycle Timing Chart (RE Control)
Cycle n tRCK tRCP RCK (Input) tRCW tAC RE (Input) tOH DOUT (Output) tOH (n) (n+1) (n+2) tREW tOH (n+3) tREN1 tRES tREH tREN2 tAC Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3
Remark OE = "L" level, RSTR = "H" level Read Cycle Timing Chart (OE Control)
Cycle n tRCK tRCP RCK (Input) tRCW tOH OE (Input) tOEW tAC tLZ DOUT (Output) High impedance (n) (n+1) tHZ (n+2) tLZ High impedance (m) tOEN1 tOES tOEH tOEN2 tAC Cycle n+1 Cycle n+2 Disable Cycle Cycle m
Remark RE = "L" level, RSTR = "H" level
Data Sheet M10060EJ7V0DS00
11
PD485506
Write Reset Cycle Timing Chart (WE = Active)
Cycle n Reset Cycle Cycle 0 Cycle 1
WCK (Input) tRN1 RSTW (Input) tRS tRSTW Note tRH tRN2
WE (Input)
"L" Level tDS tDH (n) tDS (0) tDH (1)
DIN (Input)
(n-1)
Note
In write reset cycle, reset operation is executed even without a reset cycle (tRSTW). WCK can be input any number of times in a reset cycle.
Write Reset Cycle Timing Chart (WE = Inactive)
Cycle n Reset Cycle Disable Cycle Cycle 0
WCK (Input) tRN1 RSTW (Input) tWEN1 WE (Input) tDS DIN (Input) (n-1) (n) tDH tWES tWEW tDS (0) tWEH tWEN2 tRS tRSTW Note tRH tRN2
Note
In write reset cycle, reset operation is executed even without a reset cycle (tRSTW). WCK can be input any number of times in a reset cycle.
12
Data Sheet M10060EJ7V0DS00
PD485506
Read Reset Cycle Timing Chart (RE = Active)
Cycle n Reset Cycle Cycle 0 Cycle 1
RCK (Input) tRN1 RSTR (Input) tRS tRSTR Note tRH tRN2
RE (Input)
"L" Level tAC tAC (n) tOH (0) tAC (0) tOH tAC (1) tOH
DOUT (Output)
(n - 1)
Note
In read reset cycle, reset operation is executed even without a reset cycle (tRSTR). RCK can be input any number of times in a reset cycle.
Remark OE = "L" level Read Reset Cycle Timing Chart (RE = Inactive)
Cycle n Disable Cycle Reset Cycle Cycle 0
RCK (Input) tRN1 RSTR (Input) tREN1 RE (Input) tAC DOUT (Output) (n-1) (n) tOH tAC Indefinite Data tRES tREW tAC (0) tOH tREH tREN2 tRS tRSTR Note tRH tRN2
Note
In read reset cycle, reset operation is executed even without a reset cycle (tRSTR). RCK can be input any number of times in a reset cycle.
Remark OE = "L" level
Data Sheet M10060EJ7V0DS00
13
PD485506
4. Application
4.1 1 H Delay Line
PD485506 easily allows a 1 H (5,048 bits/10,096 bits) delay line (see Figure 4.1).
Figure 4.1 1 H Delay Line Circuit
40 MHz Clock Reset
WCK Data Input 8/16 WE RSTW DIN
RCK DOUT 8/16 RE RSTR Data Output
Figure 4.2 1 H Delay Line Timing Chart
tWCK tRCK Write Read Cycle 0 tWCW tWCP tRCW tRCP Cycle 1
1H (5,048/10,096 Cycles)
2H (5,048/10,096 Cycles)
Cycle 2
Cycle 5,047Note (10,095)
Cycle 0' Cycle 0
Cycle 1' Cycle 1
Cycle 2' Cycle 2
Cycle 3' Cycle 3
WCK/RCK (Input)
tRS tRH
RSTW/ RSTR (Input)
tDS tDH (0) (1) (2) (5,046) (10,094) (5,047) (10,095) tAC
tDS tDH (0') tOH (0) (1) (2) (3) (1') (2') (3')
DIN (Input)
DOUT (Output)
Note
5,048 cycles by 16 bits/10,096 cycles by 8 bits
Remark RE, WE, OE = "L" level
14
Data Sheet M10060EJ7V0DS00
PD485506
4.2 n Bit Delay It is possible to make delay read from the write data with the PD485506. (1) Perform a reset operation in the cycle proportionate to the delay length (see Figure 4.3). (2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length (see Figure 4.4). (3) Shift the address by disabling RE for the period proportionate to the delay length (see Figure 4.5). n bit: Delay bits from write cycle to read cycle correspond to a same address cell. Restrictions Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer to 2. Operation Mode Operation-related Restriction.
MAX. Cycle Time 25 ns 35 ns MIN. MD = "L" Level 21 bits 15 bits 5,048 bits 5,048 bits MD = "H" Level 10,096 bits 10,096 bits
Figure 4.3 n-Bit Delay Line Timing Chart (1)
1H (n Cycles) 2H (n Cycles)
tWCK tRCK Write Read Cycle 0 tWCW tWCP tRCW tRCP Cycle 1
Cycle 2
Cycle (n-1)
Cycle 0' Cycle 0
Cycle 1' Cycle 1
Cycle 2' Cycle 2
Cycle 3' Cycle 3
WCK/RCK (Input)
tRS tRH
tRS tRH tDS tDH (0) (1) tWAR tDH (n-2) (n-1) tAC (0') tOH (0) (1) (2) (3) (1') (2') (3')
RSTW/ RSTR (Input)
tDS
DIN (Input)
(2)
DOUT (Output)
Remark RE, WE, OE = "L" level
Data Sheet M10060EJ7V0DS00
15
PD485506
Figure 4.4 n-Bit Delay Line Timing Chart (2)
tWCK tRCK Write Read Cycle 0 tWCW tWCP tRCW tRCP Cycle 1 Cycle 2 Cycle n-1 Cycle n Cycle 0 Cycle n+1 Cycle n+2 Cycle 1 Cycle 2 Cycle n+3 Cycle 3
WCK/RCK (Input)
tRS tRH
tWAR tRS tRH tDS tDH tDH (1) n Cycles (2) (n-2) (n-1) tAC (n) tOH (0) (1) (2) (3) (n+1) (n+2) (n+3)
RSTW (Input)
RSTR (Input) DIN (Input)
tDS
(0)
DOUT (Output)
Remark RE, WE, OE = "L" level Figure 4.5 n-Bit Delay Line Timing Chart (3)
tWCK tRCK Write Read Cycle 0 tWCW tWCP tRCW tRCP Cycle 1 Cycle 2 Cycle n-1 Cycle n Cycle 0 Cycle n+1 Cycle n+2 Cycle 1 Cycle 2 Cycle n+3 Cycle 3
WCK/RCK (Input)
tRS tRH
tWAR
RSTW/ RSTR (Input) RE (Input) DIN (Input) tDS tDH (0) (1) n Cycles DOUT (Output) (2)
tREH
tREN2
tDS tDH (n-2) (n-1) tAC (n) tOH (0) (1) (2) (3) (n+1) (n+2) (n+3)
High impedance
Remark WE, OE = "L" level
16
Data Sheet M10060EJ7V0DS00
PD485506
Figure 4.6 Mode Set Cycle Timing Chart (Write) (1)
Cycle n tMS MD (Input) Reset Cycle tMD tMH Cycle 0 Cycle 1
RSTW (Input) tRN1 WCK (Input) tDS DIN0 - DIN7 (Input) tDS DIN8 - DIN15 (Input) tDH (n-1) tDH (n-1) tDS (n) tDS (n) tDH tDH tDS (0) tDH (1) tRS tRSTW tRH tRN2
Remark WE = "L" level Figure 4.7 Mode Set Cycle Timing Chart (Write) (2)
Cycle n tMS MD (Input)
Reset Cycle tMD tMH
Cycle 0
Cycle 1
RSTW (Input) tRN1 WCK (Input) tDS DIN0 - DIN7 (Input) tDH (n-1) tDS (n) tDS DIN8 - DIN15 (Input) (0) tDH tDS (0) tDH (1) tDH (1) tRS tRSTW tRH tRN2
Remark WE = "L" level
Data Sheet M10060EJ7V0DS00
17
PD485506
Figure 4.8 Mode Set Cycle Timing Chart (Read) (1)
Cycle n tMS MD (Input) Reset Cycle tMD Cycle 0 tMH Cycle 1
RSTR (Input)
tRN1
tRS
tRSTR
tRH
tRN2
RCK (Input) tOH DOUT0 - DOUT7 (Output) (n-1)
tAC tOH (n) tAC tOH tOH (n)
tAC tOH (0) tHZM
tAC tOH (0)
tAC tOH (1)
DOUT8 - DOUT15 (Output)
(n-1)
High impedance
Remark RE, OE = "L" level Figure 4.9 Mode Set Cycle Timing Chart (Read) (2)
Cycle n tMS MD (Input) Reset Cycle tMD tMH Cycle 0 Cycle 1
RSTR (Input)
tRN1
tRS
tRSTR
tRH
tRN2
RCK (Input) tOH DOUT0 - DOUT7 (Output) (n-1)
tAC tOH (n)
tAC tOH (0) tAC tLZM tOH (0)
tAC tOH (0) tAC tOH (0)
tAC tOH (1) tAC tOH (1)
DOUT8 - DOUT15 (Output)
High impedance
Remark RE, OE = "L" level
18
Data Sheet M10060EJ7V0DS00
PD485506
4.3 Double-speed Conversion Figure 4.10 shows an example timing chart of double-speed and twice reading operation (fR = 2fW, 5,048 by 2 cycles or 10,096 by 2 cycles Note ) for a write operation (fW = 5,048 cycles or 10,096 cycles). Caution The read operation collide with the write operation on the same line, last n bits output data (5,048 -n to 5,048/10,096 -n to 10,096) in the first read operation will be undefined (see Figure 4.10 Double-speed Conversion Timing Chart). Undefined bits mentioned above depend on the cycle time.
Read Cycle Time 25 ns 35 ns Undefined Bits 21 bits 15 bits
Note
5,048 cycles by 16 bits/10,096 cycles by 8 bits
Data Sheet M10060EJ7V0DS00
19
20
1H (5,048/10,096 CyclesNote) 0 WCK (Input) 1 2 RSTW (Input) DIN (Input) 0 1 2
Data Sheet M10060EJ7V0DS00
Figure 4.10 Double-speed Conversion Timing Chart
2H (5,048/10,096 Cycles) 5,046Note 5,047 (10,094) (10,095) 0' 1' 2' 5,046' 5,047' (10,094') (10,095') 0"
5,046 5,047 (10,094) (10,095)
Note
0'
1'
2'
5,046'
5,047'
0"
(10,094') (10,095')
1H (5,048/10,096 CyclesNote) First read cycle RCK (Input)
1H (5,048/10,096 Cycles) Second read cycle
2H (5,048/10,096 Cycles) First read cycle
RSTR (Input) tAC DOUT (Output) 0 1 2
5,046 5,047
Note
0
1
2
5,046 5,047
0' 1' 2'
5,046' 5,047'
0' 1'
(10,094) (10,095)
(10,094) (10,095)
(10,094') (10,095')
n bits output data will be undefined.
n bits output data will be undefined.
Note
5,048 cycles by 16 bits/10,096 cycles by 8 bits
Remark RE, WE = "L" level
PD485506
PD485506
5. Package Drawing
44-PIN PLASTIC TSOP(II) (10.16 mm (400))
44 23 detail of lead end F
P E
1 A
22
H G S I J
C D M
M
N
S B K
L
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 18.63 MAX. 0.93 MAX. 0.8 (T.P.) 0.32 +0.08 -0.07 0.10.05 1.2 MAX. 0.97 11.760.2 10.160.1 0.80.2 0.145+0.025 -0.015 0.50.1 0.13 0.10 3+7 -3 S44G5-80-7JF5-1
Data Sheet M10060EJ7V0DS00
21
PD485506
6. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD485506. Type of Surface Mount Device
PD485506G5-7JF: 44-pin plastic TSOP (II) (10.16 mm (400))
7. Example of Stamping
Letter E in the fifth character position in a lot number signifies version E, letter K, version K, letter P, version P, letter X, version X, and letter L, version L.
JAPAN D485506

Lot number
22
Data Sheet M10060EJ7V0DS00
PD485506
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M10060EJ7V0DS00
23
PD485506
[MEMO]
* The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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